1. Field of the Invention
The present invention relates to a memory device and a memory error correction method and, more particularly, to a memory device and a memory error correction method capable of an ECC process.
2. Description of a Related Art
A soft error rate (SER) of SRAM (Static Random Access Memory) increases with the miniaturization and low-voltage operation of semiconductor devices, and it is necessary to find an early solution to this problem. The problem of increasing soft error rate is critical in general purpose memory and SRAM cells within a logic LSI. Major factors that determine SER are alpha particles emitted by component materials (such as packaging materials and aluminum lines) of semiconductor devices and high energy neutrons in secondary cosmic rays reaching the ground. Particularly, the high energy neutrons is difficult to block, and it is also difficult to perform the quantitative SER measurement of the high energy neutrons since the flux of the neutron varies depending on location on the ground and time of day.
On the other hand, the current SER of DRAM (Dynamic Random Access Memory) is improved compared to previous-generation products. However, the SER will undesirably increase also in the DRAM with the future miniaturization and low-voltage operation. Thus, the necessity to find a solution to the increasing SER will arise for the DRAM as well, at least in the near future. Besides the soft error caused by the radiation rays, device miniaturization will lead to the characteristic fluctuations of devices, including a characteristic variation by physical statistical fluctuation, a characteristic change with time, and so on. This can cause a normally operating cell to become a defective cell at some point. The characteristic fluctuations are recoverable and reversible in some cases, but are substantially unrecoverable, which is equivalent to a hard error, in other cases. Such soft errors in a broad sense are problematic.
Known as a technique to reduce the SER is to use memory with a function automatically correcting the soft errors. The memory having the automatic error correction function is referred to hereinafter as ECC (Error Check and Correct) memory. The ECC memory stores an ECC code, also called ECC (Error Correcting Code), which is redundant data for error checking and correction, and uses the ECC code to check and correct errors. Though the memory with the ECC function can automatically correct memory errors, it undesirably affects the operating time of a normal reading/writing process. To solve this problem, some techniques to reduce the effect on the operating time of the normal reading/writing process while achieving the ECC function have been developed.
For example, memory having an ECC circuit that does not perform a parity check during a data reading process but performs a parity cell read-out or an error correction during a data writing process is described in Japanese Unexamined Patent Application Publication H1-290200, for example. Specifically, this memory has a memory cell array, a horizontal parity cell array, a vertical parity cell array, an X-decoder for selecting a word line, a Y-decoder for selecting a data line, a horizontal/vertical code selection circuit, a parity check circuit of horizontal/vertical code, and an error correction circuit. In the data reading process, the readout data is output without the parity check.
In the data writing process, on the other hand, at the first voltage level of a standard clock signal, a write data signal is written into a memory cell to be written after reading out memory cell data of the horizontal and vertical codes to which the memory cell to be written belongs. At the second voltage level of the standard clock signal, a horizontal and vertical parity cell data of the horizontal and vertical codes where the memory cell for writing belongs is read out and the parity is checked using the parity cell data and the memory cell data of the horizontal and vertical codes. If an error is detected, the horizontal and vertical parity cell data is rewritten. When refreshing the memory data, the parity check on the memory cell and the parity cell and memory data error correction are performed.
In the above memory structure, since the ECC circuit does not operate during the reading process, it does not affect the operating margin of the reading process. Though the ECC circuit operates during the writing operation, it is extremely difficult for a recent high-speed device to achieve the ECC operation only in part of the writing operation time. The above prior art discloses to perform the ECC process during the refresh process, the number of cycles or a total time required for refresh increases by performing the ECC process, thus increasing a time for gaining access in a system. This causes a delay in the reading/writing operation, decreasing the system performance.
As another example, memory in which an ECC circuit operates according to operation mode and it does not operate during the normal read/write operation is disclosed in Japanese Unexamined Patent Application Publication H07-45096, for example. Specifically, this memory writes given parity information to all inspecting memory cells immediately before a data-retention state with high error rate. It is described that the parity addition can be performed during the normal operation when it does not affect memory access; however, the specific timing is not mentioned at all.
Immediately after the data-retention state, all the information memory cells are checked to detect an error location and error data, referring to the parity information in the inspecting memory cells. The timing of this operation is determined by operation mode of the memory detected by a mode detection system. However, since basically the ECC circuit does not operate during the normal operation in this memory configuration, the ECC circuit substantially does not function in memory where reading process and writing process are frequently repeated, such as high-speed devices.
As yet another example, a cell configuration having a word line, a bit line, and a transistor dedicated for refresh in addition to normal reading/writing process is disclosed in Japanese Unexamined Patent Application Publication H03-263685. However, it describes or suggests nothing about the ECC process. Further, a semiconductor device having the same memory cell configuration as DRAM and operates with SRAM specification is described in Japanese Unexamined Patent Application Publication No. 2003-85970, for example. Refreshing of the memory cells with the same configuration as DRAM is controlled according to a refresh address generated inside, and the refresh process is performed during the reading/writing cycle; thus the refresh process is not recognized from the outside. This prior art, however, does not disclose the ECC process at all.